In today's digital IC design, there is a strong need to shift delay of a clock signal to obtain phase relationship with other signals. A typical integrated circuit (IC) uses multiple individual clock signals having the same or different frequencies for operating various components of the integrated circuit. A phase error between clocks on an integrated circuit may induce performance degradation problems and functionality errors on the integrated circuit if the phase error exceeds a tolerable range. In order to minimize phase errors, the timing of a signal is set to a certain phase with respect to those clock signals on an IC or an application. However, due to the process, voltage level and temperature variations, the phase relationship may vary between similarly fabricated IC's or even among signals on a single IC. For example, the phase relationship will not remain even across chip on a single application or printed circuit board due to a temperature change.
After IC chips are fabricated and manufactured, the process of the die/chip is fixed for the IC chips. Thus timing change due the process can be compensated by one time calibration. However, the temperature and voltage in IC chips may vary after the calibration. The timing changes due to the temperature and voltage variations may affect the delay of the programmable delay cell and thus may compromise the performance of the system. Moreover, compensating for timing changes due to PVT after the calibration is difficult since the system must calibrated again to readjust the delay. In such a case, the system may have to stop its normal operation in order to calibrate. Most applications do not allow the system to stop its normal operation to perform calibrations.
Therefore, it would be advantageous to have a scheme which has ability to accurately place, adjust and continuously maintain the phase relationship between signals over PVT variations.